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| LY530AL MEMS inertial sensor single-axis analog and digital output yaw rate gyroscope Preliminary Data Features 2.7 V to 3.6 V single supply operation Low power consumption Embedded power-down 300/sec full scale Absolute analog rate output I2C/SPI digital output interface Integrated low-pass filters Additional high pass filter for digital output Embedded self-test High shock survivability ECOPACK(R) RoHS and "Green" compliant (see Section 7) The output of LY530AL has a full scale of 300 /s and is capable of measuring rates with a -3 dB bandwidth up to 88 Hz. The LY530AL is available in a plastic land grid array (LGA) package and can operate within a temperature range from -40 C to +85 C. The LY530AL belongs to a family of products suitable for a variety of applications, including: - Gaming and virtual reality input devices - Motion control with MMI (man-machine interface) - Image stabilization for digital video and digital still cameras - GPS navigation systems - Appliances and robotics LGA-16 (5x5x1.5mm) Description The LY530AL is a low-power single-axis yaw rate sensor. It includes a sensing element and an IC interface able to provide the measured angular rate to the external world through an analog output voltage and I2C/SPI digital interfaces. The sensing element, capable of detecting the yaw rate, is manufactured using a dedicated micromachining process developed by ST to produce inertial sensors and actuators on silicon wafers. The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. Table 1. Device summary Temperature range (C) -40 to +85 -40 to +85 Order code LY530AL LY530ALTR Package LGA-16 (5x5x1.5) LGA-16 (5x5x1.5) Packing Tray Tape and reel September 2008 Rev 1 1/30 www.st.com 30 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents LY530AL Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 2.4 Mechanical characteristics (analog output) . . . . . . . . . . . . . . . . . . . . . . . . 8 Mechanical characteristics (digital output) . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 2.4.2 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 2.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.1 2.6.2 2.6.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 4.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 4.2.2 4.2.3 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 6.2 6.3 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FILTER_CFG_REG (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/30 LY530AL Contents 6.4 6.5 6.6 6.7 OUTPUT_SEL_REG (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STATUS_REG(27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUT_CONV_H(28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUT_CONV_L(29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3/30 List of tables LY530AL List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mechanical characteristics @ Vdd = 3.3 V, T = 25 C unless otherwise noted . . . . . . . . . . 8 Mechanical characteristics @ Vdd = 3.3 V, T = 25 C unless otherwise noted . . . . . . . . . . 8 Electrical characteristics @ Vdd =3.3 V, T=25 C unless otherwise noted. . . . . . . . . . . . . 10 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PLL low-pass filter components' values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 19 Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19 Registers addresses map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FILTER_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FILTER_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High pass filter pole -3dB frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Low pass filter pole -3dB frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OUTPUT_SEL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OUTPUT_SEL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Filtering selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Forbidden combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STATUS_REG(27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STATUS_REG(27h) description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUT_CONV_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUT_CONV_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/30 LY530AL List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C slave timing diagram (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LY530AL electrical connections and external components values . . . . . . . . . . . . . . . . . . . 15 Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5/30 Block diagram and pin description LY530AL 1 Block diagram and pin description Figure 1. Block diagram ANALOG OUTPUT + Sens+ CHARGE AMPLIFIER DEMODULATOR SWITCHED CAPACITOR LOW-PASS FILTER ACTIVE LOW-PASS FILTER CS A/D CONVERTER CONTROL LOGIC I2C SPI SCL/SPC SDA/SDO/SDI SDO z Sens- Feedback+ TRANSIMPEDANCE AMPLIFIER ANALOG CONDITIONING FeedbackDrive- VOLTAGE GAIN AMPLIFIER Drive+ PID control AUTOMATIC GAIN CONTROL PLL SELF TEST REFERENCE TRIMMING CIRCUITS CLOCK PHASE GENERATOR 1.1 Pin description Figure 2. Pin connection VDDD VDDA Res + z SDA_SDI_SDO SDO DR CS SCL / SPC 14 13 16 1 FILTVDD VCONT CACT ANALOG OUTPUT 9 8 PD ST 5 6 GND IF_DIS (TOP VIEW) DIRECTION OF THE DETECTABLE ANGULAR RATE (BOTTOM VIEW) 6/30 LY530AL Table 2. Pin # 1 2 3 4 5 6 7 8 9 10 11 12 Block diagram and pin description Pin description Pin Name FILTVDD VCONT CACT ANALOG OUTPUT IF_DIS GND ST PD SCL SPC CS DR SDO Analog function PLL filter connection pin #2 PLL filter connection pin #1 Active filter capacitor Rate signal output voltage Leave unconnected 0V supply voltage Self-test (logic 0: normal mode; logic 1: self-test) Power-down (logic 0: normal mode; logic 1: power-down mode) Leave unconnected Leave unconnected Leave unconnected Leave unconnected or connect to Vdd Digital function PLL filter connection pin #2 PLL filter connection pin #1 Active filter capacitor Leave unconnected Digital Interface Selection (See Table 19) 0V supply voltage Leave unconnected Connect to Vdd I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI mode) DataReady SPI Serial data output (4-wire mode only) I2C less significant bit of the device address I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output Connect to Vdd Digital side Vdd supply Analog side Vdd supply 13 14 15 16 Leave unconnected or connect to SDA_SDI_SDO Vdd Res VDDD VDDA Connect to Vdd Digital side Vdd supply Analog side Vdd supply 7/30 Mechanical and electrical specifications LY530AL 2 2.1 Table 3. Symbol FS So SoDr Voff OffDr NL BW Rn Vt Sup Fres Top Wh Mechanical and electrical specifications Mechanical characteristics (analog output) Mechanical characteristics @ Vdd = 3.3 V, T = 25 C unless otherwise noted(1) Parameter Measurement range Sensitivity Sensitivity change vs. temperature Zero-rate level(3) Zero-rate level change From -40 C to +85 C vs. temperature Non linearity(4) -3dB bandwidth (5)(6) Test condition Min. Typ.(2) 300 3.3 Max. Unit /s mV/ /s % V /s % FS Hz /s / Hz mV ms kHz From -40 C to +85 C 4 1.65 5 0.8 88 0.1 +300 Best fit straight line CACT = 10 nF Rate noise density Self-test output voltage change(7) Start-up time Sensing element resonant frequency Operating temperature range Product weight -40 Settling to 5 /s 300 4.5 +85 160 C mg 1. The product is factory calibrated at 3.3 V. The operational power supply range is specified in Table 5. 2. Typical specifications are not guaranteed 3. Zero rate level is absolute with respect to power supply 4. Specified by design 5. The product is capable of sensing angular rates extending from DC to the selected bandwidth 6. User selectable by external capacitor CACT 7. "Self-test output voltage change" is defined as Vout(Vst = logic 1) - Vout(Vst = logic 0) 2.2 Table 4. Symbol So Voff ODR Mechanical characteristics (digital output) Mechanical characteristics @ Vdd = 3.3 V, T = 25 C unless otherwise noted(1) Parameter Sensitivity Zero-rate level (3) Test condition Min. Typ.(2) 1.55 0 1 Max. Unit LSb/ /s LSb kHz Output data rate 8/30 LY530AL Table 4. Symbol Vt Fres Top Wh Mechanical and electrical specifications Mechanical characteristics @ Vdd = 3.3 V, T = 25 C unless otherwise noted(1) Parameter Self-test output change(4) Sensing element resonant frequency Operating temperature range Product weight -40 160 Test condition Min. Typ.(2) 230 4.5 +85 Max. Unit LSb kHz C mg 1. The product is factory calibrated at 3.3 V. The operational power supply range is specified in Table 5. 2. Typical specifications are not guaranteed 3. The product is capable of sensing angular rates extending from DC to the selected bandwidth 4. "Self test output change" is defined as OUTPUT[LSb](Self-test bit on OUTPUT_SEL_REG=1) OUTPUT[LSb](Self-test bit on OUTPUT_SEL_REG=0). 9/30 Mechanical and electrical specifications LY530AL 2.3 Table 5. Symbol Vdd Idd_A Idd_D IddPdn Electrical characteristics Electrical characteristics @ Vdd =3.3 V, T=25 C unless otherwise noted(1) Parameter Supply voltage Supply current (analog) Supply current (digital) Supply current in power-down mode Self-test input (Analog use) Power-down input (Analog use) Active low-pass filter capacitor Output voltage swing(3) Capacitive load drive(3) Iout = 100A PD pin connected to Vdd Logic 0 level Logic 1 level Logic 0 level Logic 1 level 0 0.8*Vdd 0 0.8*Vdd 10 0.4 0.4 -40 Vdd-0.4 10 +85 PD pin connected to GND Test condition Min. 2.7 Typ.(2) 3.3 4.8 5.5 1 0.2*Vdd V Vdd 0.2*Vdd V Vdd nF V nF C Max. 3.6 Unit V mA mA A VST VPD CACT OVS CLOAD Top Operating temperature range 1. The product is factory calibrated at 3.3 V 2. Typical specifications are not guaranteed 3. Referred to ANALOG OUTPUT pin #6 10/30 LY530AL Mechanical and electrical specifications 2.4 2.4.1 Communication interface characteristics SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6. SPI slave timing values Value(1) Parameter Min Max ns 10 5 8 5 15 50 6 50 ns MHz SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 100 Unit Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 3. SPI slave timing diagram (2) CS (3) (3) tsu(CS) tc(SPC) th(CS) (3) SPC (3) tsu(SI) th(SI) MSB IN LSB IN (3) SDI (3) tv(SO) th(SO) LSB OUT tdis(SO) (3) SDO (3) MSB OUT 2. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both Input and Output port 3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors 11/30 Mechanical and electrical specifications LY530AL 2.4.2 I2C - Inter IC control interface Subject to general operating conditions for Vdd and Top. Table 7. Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) I2C slave timing values I2C Standard mode(1) Parameter Min SCL clock frequency SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 4 4.7 4 4.7 0 4.7 4.0 250 0(2) 3.45 1000 300 Max 100 Min 0 1.3 s 0.6 100 0(2) 20 + 0.1Cb (3) 20 + 0.1Cb (3) 0.6 0.6 s 0.6 1.3 0.9 300 ns 300 ns s Max 400 KHz I2C Fast mode (1) Unit tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(ST) tsu(SR) tsu(SP) tw(SP:SR) 1. Data based on standard I2C protocol requirement, not tested in production 2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL 3. Cb = total capacitance of one bus line, in pF Figure 4. I2C slave timing diagram (4) REPEATED START START tsu(SR) SDA tw(SP:SR) START tf(SDA) tr(SDA) tsu(SDA) th(SDA) tsu(SP) STOP SCL th(ST) tw(SCLL) tw(SCLH) tr(SCL) tf(SCL) 4. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both ports 12/30 LY530AL Mechanical and electrical specifications 2.5 Absolute maximum ratings Stresses above those listed as "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8. Symbol Vdd Vin AUNP TSTG ESD Supply voltage Input voltage on any control pin (PD, ST) Acceleration (not powered) 10000 g for 0.1 ms Storage temperature range Electrostatic discharge protection -40 to +125 2 (HBM) C kV Absolute maximum ratings Ratings Maximum value -0.3 to 6 -0.3 to Vdd +0.3 3000 g for 0.5 ms Unit V V This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part This is an ESD sensitive device, improper handling can cause permanent damage to the part 13/30 Mechanical and electrical specifications LY530AL 2.6 2.6.1 Terminology Sensitivity A yaw rate gyroscope is a Z-axis rate device that produces a positive-going output value for counterclockwise rotation around the axis normal to the package top. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and also very little over time. 2.6.2 Zero-rate level Zero-rate level describes the actual output value if there is no angular rate present.Zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and also very little over time. 2.6.3 Self-test Self-test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. If the device is used as analog component the Self-test function is off when the ST pin is connected to GND. When the ST pin is tied to Vdd, an actuation force is applied to the sensor, emulating a definite Coriolis force. In this case the sensor output will exhibit a voltage change in its DC level which is also depending on the supply voltage. For the digital use of the device, the self test function is enabled acting on ST_bit inside OUTPUT_SEL_REG(23h). When ST is active, the device output level is given by the algebraic sum of the signals produced by the velocity acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Table 3, then the mechanical element is working properly and the parameters of the interface chip are within the defined specification. 14/30 LY530AL Application hints 3 Application hints Figure 5. + z 9nF 9.5kOhm LY530AL electrical9nF connections and external components values C2 450nF GND GND VDDA VDDD GND GND R1 C1 10 F 100 nF 100 nF 10 F 1 Optional Low-pass filter ROPT CACT 16 14 13 SDA_SDI_SDO SDO LY530AL (Top View) 5 9 DR CS VoutYAW COPT GND 0.4nF CLOAD GND 6 8 SCL/SPC ST IF_DIS Digital signals Power supply decoupling capacitors (100 nF ceramic or polyester + 10 F Aluminum) should be placed as near as possible to the device (common design practice). VDDA(pin 16) and VDDD(pin 15) lines have been kept separated to avoid switching noise coupling on the analog side. The LY530AL allows to band limit the output rate response through the use of two first-order on-chip filters: a switched capacitor low-pass filter, with 400Hz -3dB bandwidth, in combination with an active low-pass filter. The active filter -3 dB nominal frequency (ftA) is set through an internal resistor RACT and the external capacitor CACT (added between CACT pin #3 and ANALOG OUTPUT pin #4), by the formula: 1 f tA = -------------------------------------------------2 R ACT C ACT The value of the internal resistor RACT is 180 k while the external capacitor CACT is used to , select the signal bandwidth. The sensed frequency range spans from DC up to the selected bandwidth. In order to further reduce high-frequency noise, the LY530AL supports an additional optional low-pass filter on ANALOG OUTPUT pin #4 (Figure 5). The cutoff frequency (ftP) is given by the formula: PD GND 15/30 Application hints LY530AL 1 f tP = --------------------------------------------------2 R OPT C OPT The LY530AL IC includes a PLL (phase locked loop) circuit to synchronize driving and sensing interfaces. Capacitors and resistors must be added at the FILTVDD and VCONT pins (as shown in Figure 5) to implement a second-order low-pass filter. Table 9 summarizes the PLL low-pass filter components' values. Table 9. PLL low-pass filter components' values Component C1 C2 R1 Value 450 nF 10% 9 nF 10% 9.5 k 10% 3.1 Soldering information The LGA package is compliant with the ECOPACK(R), RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Leave "Pin 1 Indicator" unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems. 16/30 LY530AL Digital interfaces 4 Digital interfaces The registers embedded inside the LY530AL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd_IO). Table 10. Serial interface pin description Pin description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO) I2C less significant bit of the device address Pin name CS SCL/SPC SDA/SDI/SDO SDO 4.1 I2C serial interface The LY530AL I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 11. Term Transmitter Receiver Master Slave I2C terminology Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LY530AL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the normal mode. 17/30 Digital interfaces LY530AL 4.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LY530AL is 110100xb. SDO pin can be used to modify less significant bit of the device address. If SDO pin is connected to voltage supply LSb is `1' (address 1101001b) else if SDO pin is connected to ground LSb value is `0' (address 1101000b). This solution permits to connect and address two different gyroscopes to the same I2C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the LY530AL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was `1' (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is `0' (Write) the Master will transmit to the slave with direction unchanged. Table explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 12. SAD+Read/Write patterns SAD[6:1] 110100 110100 110100 110100 SAD[0] = SDO 0 0 1 1 R/W 1 0 1 0 SAD+R/W 11010001 (39h) 11010000 (38h) 11010011 (3Bh) 11010010 (3Ah) Command Read Write Read Write Table 13. Master Slave Transfer when Master is writing one byte to slave ST SAD + W SAK SUB SAK DATA SAK SP 18/30 LY530AL Digital interfaces Table 14. Master Slave Transfer when Master is writing multiple bytes to slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP Table 15. Master Slave ST Transfer when Master is receiving (reading) one byte of data from slave SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP Table 16. Master Slave Transfer when Master is receiving (reading) multiple bytes of data from slave ST SAD+W SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 4.2 SPI bus interface The LY530AL SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. 19/30 Digital interfaces Figure 6. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 LY530AL Read & write protocol SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged. 20/30 LY530AL Digital interfaces 4.2.1 SPI read Figure 7. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 8. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 Multiple bytes SPI read protocol (2 bytes example) SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 4.2.2 SPI write Figure 9. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SPI write protocol 21/30 Digital interfaces LY530AL The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 10. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 4.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode. 22/30 LY530AL Register mapping 5 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 17. Registers addresses map Register address Name Type Hex Binary Reserved 000 1111 11010001 Dummy register Reserved 010 0000 00000000 010 0001 010 0010 010 0011 00000000 001 1000 001 1001 001 1010 010 0111 00000000 010 1000 010 1001 Reserved Reserved Reserved Reserved Loaded at boot 00-0E r 0F 10-1F rw 20 21 rw rw 22 23 24 25 26 r r r 27 28 29 Default Comment Reserved (do not modify) WHO_AM_I Reserved (do not modify) CTRL_REG Reserved (do not modify) FILTER_CFG_REG OUTPUT_SEL_REG Reserved (do not modify) Reserved (do not modify) Reserved (do not modify) STATUS_REG OUT_CONV_H OUT_CONV_L Registers marked as "Reserved" or not listed must not be changed. The writing to those registers may cause permanent damages to the device. 23/30 Register description LY530AL 6 Register description The device contains a set of registers which are used to control its behavior and to retrieve angular rate data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 6.1 WHO_AM_I (0Fh) Table 18. 1 WHO_AM_I register 1 0 1 0 0 0 1 Device identification register. This register contains the device identifier that for LY530AL is set to D1h 6.2 CTRL_REG (20h) Table 19. TUD_SDO CTRL_REG register DIG_en 0(1) IF_SEL BDU alg BOOT SIM 1. `0' is the default value. This value must not be changed Table 20. TUD_SDO DIG_en IF_SEL BDU alg BOOT SIM CTRL_REG description Pull Up disable for SDO pin. Default value: 0 (0: Pull Up connected; 1: Pull Up disabled) Power Down bit. Default value: 0 (0: Device is in power down mode; 1: Divice is in normal mode) Interface selection. Default value: 0 (0: both interfaces available; 1: IF_DIS pin value selects the interface) Block data update. Default value: 0 (0: continuos update; 1: update inhibited) Data alignment selection bit. Default value: 0 (0: 16 bit left justified; 1: 10 bit right justified) Reboot of memory content. Default value: 0 (0: normal mode; 1: memory reboot) SPI serial interface mode selection bit. Default value: 0 (0: 4-wire mode; 1:3-wire mode) TUD_SDO: When this bit is set to `1' the Pull Up on SDO pin is disabled. DIG_en: When this bit is set to `1' the device is in normal mode. When DIG_en bit is `0' the device is in power down mode. IF_SEL: Setting this bit to `1' the voltage value applied to IF_DIS pin selects one of the two digital interfaces (`1' for I2C only, `0' for SPI only). 24/30 LY530AL Register description BDU: This bit is used to inhibit output registers update until both upper and lower parts are read. In default mode (BDU='0') the output registers values are updated continuosly. It is recommended to set BDU bit to `1' if the reading is not faster than the output data rate. alg: This bit permits to decide between 16 bits left justified (default value) and 10 bits right justified representation of data coming from the device. In this last case the most significant bits are replaced by the bit representing the sign. BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to `1' the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every gyroscope. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to `0'. SIM bit selects the SPI Serial Interface Mode. When SIM is `0' (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pin. In 3-wire interface mode output data are sent to SDA/SDI/SDO pin. 6.3 FILTER_CFG_REG (22h) Table 21. HP_BW1 FILTER_CFG_REG register HP_BW0 LP_BW2 LP_BW1 LP_BW0 0 (1) 0 0 1. 0 is the default value loaded at boot. This value must not be changed. Table 22. HP_BW(1-0) LP_BW(2-0) FILTER_CFG_REG description High pass filter pole frequency selection Low pass filter pole frequency selection Table 23. High pass filter pole -3dB frequency selection HP_BW[1:0] 00 01 10 11 Pole frequency [Hz] 1.25 0.31 0.15 0.08 Table 24. Low pass filter pole -3dB frequency selection LP_BW[2:0] 000 001 010 Pole frequency [Hz] 115 46.1 21.3 25/30 Register description Table 24. Low pass filter pole -3dB frequency selection (continued) LP_BW[2:0] 011 100 101 110 111 Pole frequency [Hz] 10.3 5.1 2.5 1.2 0.6 LY530AL 6.4 OUTPUT_SEL_REG (23h) Table 25. X OUTPUT_SEL_REG register X ST_bit X X OUT2 OUT1 OUT0 Table 26. ST_bit OUT2-0 OUTPUT_SEL_REG description When Dig_en is set to `1', ST_bit enables Selft Test function. Default value: 0 (0: no selft test activated; 1: self test enabled Output data filtering selection Table 27. Filtering selection Filter type no filtering high pass 2 x high pass low pass high pass + low pass 2 x high pass + low pass OUTPUT_SEL_REG[2:0] 000 001 011 100 101 111 Table 28. Forbidden combinations OUTPUT_SEL_REG[2:0] 111 100 111 101 101 100 FILTER_CFG_REG[2:0] 101 101 100 100 111 111 26/30 LY530AL Register description 6.5 STATUS_REG(27h) Table 29. X(1) 1. Undefined value STATUS_REG(27h) register X X X X ow davbH davbL Table 30. ow davbH davbL STATUS_REG(27h) description Digital data overrun. When `1', output registers have been updated before being read. When this bit is `1', new data is available on OUT_CONV_H (high part) When this bit is `1', new data is available on OUT_CONV_L (low part) 6.6 OUT_CONV_H(28h) Table 31. DOH7 OUT_CONV_H register DOH6 DOH5 DOH4 DOH3 DOH2 DOH1 DOH0 These bits are the high part of digital output expressed as 2's complement number. For data alignment see alg bit in CTRL_REG(20h) (Table 20). 6.7 OUT_CONV_L(29h) Table 32. DOL7 OUT_CONV_L register DOL6 DOL5 DOL4 DOL3 DOL2 DOL1 DOL0 These bits are the lowpart of digital output expressed as 2's complement number. For data alignment see alg bit in CTRL_REG(20h) (Table 20). 27/30 Package information LY530AL 7 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK(R) is an ST trademark. ECOPACK(R) specifications are available at: www.st.com. Figure 12. LGA-16: mechanical data and package dimensions A1 A2 A3 C D1 E1 L L1 M M1 M2 N N1 T1 T2 R S h k j 1.46 1.5 1.6 1.33 0.057 0.059 0.063 0.052 0.16 0.2 0.3 0.24 0.006 0.008 0.012 0.009 4.85 4.85 5 5 0.8 3.2 1.6 5.15 5.15 0.191 0.191 0.197 0.197 0.031 0.126 0.062 0.203 0.203 2.15 2.175 1.625 2.175 2.4 0.8 2.20 0.085 0.086 0.064 0.086 0.094 0.031 0.087 LGA-16 (5x5x1.6mm) Land Grid Array Package 0.021 0.063 0.475 1.2 0.5 0.525 1.6 0.019 0.047 0.020 0.1 0.15 0.05 0.1 0.004 0.006 0.002 0.004 7887555A 28/30 LY530AL Revision history 8 Revision history Table 33. Date 03-Sep-2008 Document revision history Revision 1 Initial release Changes 29/30 LY530AL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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